The present invention relates, in general, to digital transceivers and, more particularly, to a digital transmitter using a fractional-N frequency synthesizer.
Phase-Locked Loop (PLL) frequency synthesis is a well known technique for generating one of many related signals from a Voltage Controlled Oscillator (VCO). In a PLL, an output signal from the VCO is coupled to a programmable frequency divider which divides by a selected integer number. A phase detector compares the frequency divided signal to a reference signal and any difference in phase between the frequency divided signal and the reference signal is output from the phase detector, coupled through a loop filter, and applied to the VCO. The VCO provides an output signal that changes in frequency such that the phase error between the frequency divided signal and the reference signal is minimized.
In order to overcome the limitations of the output frequency step size being constrained to be equal to the reference signal frequency, a fractional-N synthesizer having programmable frequency dividers capable of dividing by non-integers has been developed. Output frequency step sizes which are fractions of the reference signal frequency are obtained while maintaining a high reference frequency and wide loop bandwidth. A transmitter that includes a fractional-N synthesizer has been used to provide a phase modulation signal for Global System for Mobil communications (GSM). However, other communications protocols such as Time Division Multiple Access (TDMA) and Code Division Multiple Access (CDMA) require amplitude modulation in addition to the phase modulation.
Hence, a need exists for a transmitter capable of operating over a wide frequency band, while providing an RF modulated output signal having both amplitude modulation and phase modulation.